Proposal #77·Accepted
Verilog HDL implementation of graph accelerator for Retinex Model—Code Package Release
Disease: Fundamental Research
Proposer: 0x6b4A…8A5B
Summary
A complete HDL code package including the implementation of the complete accelerator proposed in period 33 is included in this submission. Each piece of Verilog code implements a section of the processing element within an accelerator. In addition, wiring is performed to assemble the entire processing element to form a complete processing element array. Finally, various testbench was written to test and debug our implementation. The team will compile an in-depth documentation for this work following this submission.
Full content (IPFS)open on IPFS ↗
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